參數(shù)資料
型號(hào): MCF5213LCVM66J
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 27/56頁(yè)
文件大?。?/td> 0K
描述: IC MCU 256K FLASH 66MHZ 81MAPBGA
標(biāo)準(zhǔn)包裝: 240
系列: MCF521x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 66MHz
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 81-LBGA
包裝: 托盤(pán)
Electrical Characteristics
MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
33
2.8
General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, timer, UART, and Interrupt interfaces. When in GPIO mode,
the timing specification for these pins is given in Table 28 and Figure 5.
The GPIO timing is met under the following load test conditions:
50 pF / 50
Ω for high drive
25 pF / 25
Ω for low drive
Frequency un-LOCK range
fUL
–1.5
1.5
% fref
Frequency LOCK range
fLCK
–0.75
0.75
% fref
CLKOUT period jitter 4, 5, 8 ,9, measured at fSYS Max
Peak-to-peak (clock edge to clock edge)
Long term (averaged over 2 ms interval)
Cjitter
10
.01
% fsys
On-chip oscillator frequency
foco
7.84
8.16
MHz
1 All internal registers retain data at 0 Hz.
2 Depending on packaging; see Table 2.
3 Loss of Reference Frequency is the reference frequency detected internally, which transitions the PLL into self clocked mode.
4 Self clocked mode frequency is the frequency at which the PLL operates when the reference frequency falls below f
LOR with
default MFD/RFD settings.
5 This parameter is characterized before qualification rather than 100% tested.
6 Proper PC board layout procedures must be followed to achieve specifications.
7 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the Cjitter percentage
for a given interval.
9 Based on slow system clock of 40 MHz measured at f
sys max.
Table 28. GPIO Timing
NUM
Characteristic
Symbol
Min
Max
Unit
G1
CLKOUT High to GPIO Output Valid
tCHPOV
—10
ns
G2
CLKOUT High to GPIO Output Invalid
tCHPOI
1.5
ns
G3
GPIO Input Valid to CLKOUT High
tPVCH
9—
ns
G4
CLKOUT High to GPIO Input Invalid
tCHPI
1.5
ns
Table 27. PLL Electrical Specifications (continued)
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V)
Characteristic
Symbol
Min
Max
Unit
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