參數(shù)資料
型號(hào): MCF5208_07
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Microprocessor Data Sheet
中文描述: 微處理器數(shù)據(jù)表
文件頁(yè)數(shù): 44/46頁(yè)
文件大小: 480K
代理商: MCF5208_07
MCF5208 ColdFire
Microprocessor Data Sheet, Rev. 1
Revision History
6
Freescale Semiconductor
44
Revision History
Table 26. Revision History
Revision
Number
Date
Substantive Changes
0
5/23/2005
Initial Release
0.1
6/16/2005
Corrected 144QFP pinout in
Figure 1
. Pins 139-142 incorrectly showed
FEC functionality, which are actually UART 0/1 clear-to-send and
request-to-send signals.
Changed maximum core frequency in
Table 10
, spec #2, from 240MHz to
166.67MHz. Also, changed symbols in table: f
core
-> f
sys
and f
sys
-> f
sys/2
for consistency throughout document and reference manual.
0.2
8/26/2005
Changed ball M9 from SD_VDD to EVDD in
Figure 9
.
Table 3
: Pin 33 for 144 LQFP package should be EVDD instead of
SD_VDD. BE/BWE[3:0] for 144 LQFP should be “20, 48, 18, 50“ instead
of “18, 20, 48, 50”
Cleaned up various electrical specifications:
Table 4
: Added DDR/Memory pad supply voltage spec, changed “clock
synthesizer supply voltage” to “PLL supply voltage”, changed min PLLV
DD
from -0.5 to -0.3, changed max V
IN
from 4.0 to 3.6, changed minimum T
stg
from -65 to -55,
Table 5
: Changed TBD values in T
j
entry to 105
°
C.
Table 7
: Changed minimum core supply voltage from 1.35 to 1.4 and
maximum from 1.65 to 1.6, added PLL supply voltage entry, added pad
supply entries for mobile-DDR, DDR, and SDR, changed minimum input
high voltage from 0.7xEV
DD
to 2 and maximum from 3.65 to EV
DD
+0.05,
changed minimum input low voltage from VSS-0.3 to -0.05 and maximum
from 0.35xEV
DD
to 0.8, added input high/low voltage entries for DDR and
mobile-DDR, removed high impedance leakage current entry, changed
minimum output high voltage from EV
DD
-0.5 to EV
DD
-0.4, added DDR/bus
output high/low voltage entries, removed load capacitance and DC
injection current entries.
Added filtering circuits and voltage sequencing sections:
Section 5.4.1,
“PLL Power Filtering,”
and
Section 5.4.2, “Supply Voltage Sequencing and
Separation Cautions.”
Removed “Operating Conditions” table from
Section 5.6, “Oscillator and
PLL Electrical Characteristics,”
because it is redundant with
Table 7
.
Table 11
: Changed minimum core frequency to TBD, removed external
reference and on-chip PLL frequency specs to have only a CLKOUT
frequency spec of TBD to 83.33MHz, removed loss of reference frequency
and self-clocked mode frequency entries, in EXTAL input high/low voltage
entries changed “All other modes (Dual controller (1:1), Bypass, External)”
to “All other modes (External, Limp)”, removed XTAL output high/low
voltage entries, removed power-up to lock time entry, removed last 5
entries (frequency un-lock range, frequency lock range, CLKOUT period
jitter, frequency modulation range limit, and ICO frequency)
0.3
9/07/2005
Corrected DRAMSEL footnote #3 in
Table 3
.
Updated
Table 3
with 144MAPBGA pin locations.
Added 144MAPBGA ballmap to
Section 4.3, “Pinout—144 MAPBGA.”
Changed J12 from PLL_VDD to IVDD in
Figure 9
.
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