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| 型號： | MCAQE32G8APP-0XA |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PQFP |
| 封裝： | LQFP |
| 文件頁數(shù)： | 16/62頁 |
| 文件大?。?/td> | 740K |
| 代理商： | MCAQE32G8APP-0XA |
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NAND Flash-based Solid State Disk
23
Nov. 15. 2006
Figure 7 through Figure 16 define the timings associated with all phases of Ultra DMA bursts.
Table 4 contains the values for the timings for each of the Ultra DMA modes.
Table 4 - Ultra DMA data burst timing requirements
NOTE:
1. Timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies. For example, the sender shall stop
generating STROBE edges tRFS after the negation of DMARDY-. Both STROBE and DMARDY- timing measurements are taken at the connector of the
sender.
2. All timing measurement switching points(low to high and high to low) shall be taken at 1.5V.
3. tUI, tMLI, and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is waiting for the other to respond with a
signal before proceeding. tUI is an inlimited interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a lim-
ited time-out that has a defined maximum.
4. The test load for tDVS and tDVH shall be a lumped capacitor load with no cable or receivers. Timing for tDVS and tDVH shall be met for all capacitive
loads from 15 to 40 pf where all signals have the same capacitive load value.
5. tZIORDY may be greater than tENV since the device has a pull up on IORDY- giving it a known state when released.
Name
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Comment
(See Notes 1 and 2)
min
max
min
max
min
max
min
max
min
max
t2CYCTYP 240
160
120
90
60
Typical sustained average two cycle time
tCYC
112
7354
3925
Cycle time allowing for asymmetry and clock varia-
tions (from STROBE edge to STROBE edge)
t2CYC
230
154
115
86
57
Two cycle time allowing for clock variations (from ris-
ing edge to next rising edge or from falling edge to
next falling edge of STROBE)
tDS
15
10
7
5
Data setup time at recipient
tDH
5
Data hold time at recipient
tDVS
70
48
30
20
6
Data valid setup time at sender (from data valid until
STROBE edge) (See Note 4)
tDVH
666
66
Data valid hold time at sender (from STROBE edge
until data may become invalid) (See Note 4)
tFS
0
230
0
200
0
170
0
130
0
120
First STROBE time (for device to first negate
DSTROBE from STOP during a data in burst)
tLI
0
150
0
150
0
150
0
100
0
100 Limited interlock time (See Note 3)
tMLI
20
Interlock time with minimum(See Note 3)
tUI
0
Unlimited interlock time (See Note 3)
tAZ
10
Maximum time allowed for output drivers to release
(from asserted or negated)
tZAH
20
Minimum delay time required for output
tZAD
0
Drivers to assert or negate (from released)
tENV
20
70
20
70
20
70
20
55
20
55
Envelope
time
(from
DMACK-
to
STOP
and
HDMARDY- during data in burst initiation and from
DMACK to STOP during data out burst initiation)
tSR
50
30
20
NA
STROBE-to-DMARDY- time (if DMARDY- is negated
before this long after STROBE edge, the recipient
shall receive no more than one additional data word)
tRFS
75
70
60
Ready-to-final-STROBE time (no STROBE edges
shall be sent this long after negation of DMARDY-)
tRP
160
125
100
Minimum time to assert STOP or negate DMARQ
tIORDYZ
20
Maximum time before releasing IORDY
tZIORDY
0
Minimum time before driving STROBE (See Note 5)
tACK
20
Setup and hold times for DMACK- (before assertion
or negation)
tSS
50
Time from STROBE edge to negation of DMARQ or
assertion of STOP (when sender terminates a burst)
4.6.4 Ultra DMA data burst
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