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| 型號： | MC9SD64VFUR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 86/102頁 |
| 文件大?。?/td> | 1007K |
| 代理商： | MC9SD64VFUR2 |
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MC9S12DJ64 Device User Guide — V01.02
84
The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50.
ζ = 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above inputs the resistance can be calculated as:
The capacitance Cs can now be calculated as:
The capacitance Cp should be chosen in the range of:
The stabilization delays shown in Table A-16 are dependant on PLL operational settings and external
component selection (e.g. crystal, XFC filter).
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the
deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
f
C
2
ζ f
ref
πζ
1
ζ
2
+
------------------------------------------
1
50
------
f
C
f
ref
450
--------------
ζ 0.9
=
(
)
;
<
→
<
n
f
VCO
f
ref
-------------
2
synr
1
+
()
==
R
2
π nf
C
KΦ
-----------------------------
=
C
s
2
ζ
2
π f
C R
----------------------
0.516
f
C R
---------------
ζ 0.9
=
()
;
≈
=
C
s 20
C
p
C
s 10
≤≤
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