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參數(shù)資料
| 型號： | MC9SA256BCFUR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 10/102頁 |
| 文件大?。?/td> | 1050K |
| 代理商： | MC9SA256BCFUR2 |
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MC9S12A256 Device Guide — V01.01
15
Section 1 Introduction
1.1 Overview
The MC9S12A256 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 256K bytes of Flash EEPROM, 12K
bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three
serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit
analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), 29 discrete digital I/O
channels (Port A, Port B, Port K and Port E), 20 discrete digital I/O lines with interrupt and wakeup
capability and an Inter-IC Bus. System resource mapping, clock generation, interrupt control and bus
interfacing are managed by the System Integration Module (SIM). The MC9S12A256 has full 16-bit data
paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide
memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power
consumption and performance to be adjusted to suit operational requirements.
1.2 Features
HCS12 Core
–
16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii. Instruction queue
iv. Enhanced indexed addressing
–
MEBI (Multiplexed External Bus Interface)
–
MMC (Module Mapping Control)
–
INT (Interrupt control)
–
BKP (Breakpoints)
–
BDM (Background Debug Mode)
CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor)
8-bit and 4-bit ports with interrupt functionality
–
Digital filtering
–
Programmable rising or falling edge trigger
Memory
–
256K Flash EEPROM
–
4K byte EEPROM
–
12K byte RAM
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