
Chapter 11 Memory Mapping Control (S12XMMCV4) SUPPORTING FLEXRAY
MC9S12XF - Family Reference Manual, Rev.1.17
Freescale Semiconductor
481
A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the
misaligned word access is not a PRR, the access will take only 3 cycles.
A byte access to a PRR will take 2 cycles.
Table 11-20. PRR Listing
PRR Name
PRR Local Address
PRR Location
PORTA
0x0000
PIM
PORTB
0x0001
PIM
DDRA
0x0002
PIM
DDRB
0x0003
PIM
PORTC
0x0004
PIM
PORTD
0x0005
PIM
DDRC
0x0006
PIM
DDRD
0x0007
PIM
PORTE
0x0008
PIM
DDRE
0x0009
PIM
MMCCTL0
0x000A
MMC
MODE
0x000B
MMC
PUCR
0x000C
PIM
RDRIV
0x000D
PIM
EBICTL0
0x000E
EBI
EBICTL1
0x000F
EBI
Reserved
0x0012
MMC
MMCCTL1
0x0013
MMC
ECLKCTL
0x001C
PIM
Reserved
0x001D
PIM
PORTK
0x0032
PIM
DDRK
0x0033
PIM