
Appendix A Electrical Characteristics
MC9S12XF - Family Reference Manual, Rev.1.17
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Freescale Semiconductor
A.6.3
Phase Locked Loop
A.6.3.1
Jitter Information
With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input
voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes
in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the
control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as
Figure A-5. Jitter Denitions
The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
2
3
N-1
N
1
0
tnom
tmax1
tmin1
tmaxN
tminN