
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
MC9S12XE-Family Reference Manual Rev. 1.21
Freescale Semiconductor
711
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
and the counter value and causes the state of the output to change during the period. The starting polarity
of the output is also selectable on a per channel basis. Shown below in
Figure 19-19 is the block diagram
for the PWM timer.
Figure 19-19. PWM Timer Channel Block Diagram
19.4.2.1
PWM Enable
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual
PWM waveform is not available on the associated PWM output until its clock source begins its next cycle
due to the synchronization of PWMEx and the clock source. An exception to this is when channels are
NOTE
The rst PWM cycle after enabling the channel can be irregular.
On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high.
There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an
edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count.
Clock Source
T
R
Q
PPOLx
From Port PWMP
Data Register
PWMEx
To Pin
Driver
Gate
8-bit Compare =
PWMDTYx
8-bit Compare =
PWMPERx
CAEx
T
R
Q
8-Bit Counter
PWMCNTx
M
U
X
M
U
X
(Clock Edge
Sync)
Up/Down
Reset