
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
340
Freescale Semiconductor
7.3.2.22
Delay Counter Control Register (DLYCT)
Read: Anytime
Write: Anytime
All bits reset to zero.
76543210
R
DLY7
DLY6
DLY5
DLY4
DLY3
DLY2
DLY1
DLY0
W
Reset
00000000
Figure 7-44. Delay Counter Control Register (DLYCT)
Table 7-26. DLYCT Field Descriptions
Field
Description
7:0
DLY[7:0]
Delay Counter Select — When the PRNT bit of TSCR1 register is set to 0, only bits DLY0, DLY1 are used to
calculate the delay.
Table 7-27 shows the delay settings in this case.
When the PRNT bit of TSCR1 register is set to 1, all bits are used to set a more precise delay.
Table 7-28 shows
the delay settings in this case. After detection of a valid edge on an input capture pin, the delay counter counts
the pre-selected number of [(dly_cnt + 1)*4]bus clock cycles, then it will generate a pulse on its output if the level
of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid reaction to
narrow input pulses.
Delay between two active edges of the input signal period should be longer than the selected counter delay.
Note: It is recommended to not write to this register while the timer is enabled, that is when TEN is set in register
TSCR1.
Table 7-27. Delay Counter Select when PRNT = 0
DLY1
DLY0
Delay
0
Disabled
0
1
256 bus clock cycles
1
0
512 bus clock cycles
1
1024 bus clock cycles
Table 7-28. Delay Counter Select Examples when PRNT = 1
DLY7
DLY6
DLY5
DLY4
DLY3
DLY2
DLY1
DLY0
Delay
00000000
Disabled (bypassed)
00000001
8 bus clock cycles
00000010
12 bus clock cycles
00000011
16 bus clock cycles
00000100
20 bus clock cycles
00000101
24 bus clock cycles
00000110
28 bus clock cycles
00000111
32 bus clock cycles
00001111
64 bus clock cycles
00011111
128 bus clock cycles
00111111
256 bus clock cycles
01111111
512 bus clock cycles
11111111
1024 bus clock cycles