
Appendix A Electrical Characteristics
MC9S12XDP512 Data Sheet, Rev. 2.21
1274
Freescale Semiconductor
A.7
SPI Timing
This section provides electrical parametrics and ratings for the SPI. In
Table A-25 the measurement
conditions are listed.
A.7.1
Master Mode
In
Figure A-6 the timing diagram for master mode with transmission format CPHA = 0 is depicted.
Figure A-6. SPI Master Timing (CPHA = 0)
In
Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted.
Table A-25. Measurement Conditions
Description
Value
Unit
Drive mode
Full drive mode
—
Load capacitance CLOAD
1
, on all outputs
1 Timing specied for equal load on all SPI output pins. Avoid asymmetric load.
50
pF
Thresholds for delay measurement points
(20% / 80%) VDDX
V
SCK
(Output)
SCK
(Output)
MISO
(Input)
MOSI
(Output)
SS1
(Output)
1
9
5
6
MSB IN2
Bit 6 . . . 1
LSB IN
MSB OUT2
LSB OUT
Bit 6 . . . 1
11
4
2
10
(CPOL = 0)
(CPOL = 1)
3
13
1. If congured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12