
Chapter 6 XGATE (S12XGATEV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
227
Operation
RS1[(o+w):o]
RD[w:0]; 0 RD[15:(w+1)]
w = (RS2[7:4])
o = (RS2[3:0])
Extracts w+1 bits from register RS1 starting at position o and writes them right aligned into register RD.
The remaining bits in RD will be cleared. If (o+w) > 15 only bits [15:o] get extracted.
CCR Effects
Code and CPU Cycles
BFEXT
Bit Field Extract
BFEXT
NZ
V
C
0
0
N:
Set if bit 15 of the result is set; cleared otherwise.
Z:
Set if the result is $0000; cleared otherwise.
V:
0; cleared.
C:
Not affected.
Source Form
Address
Mode
Machine Code
Cycles
BFEXT RD, RS1, RS2
TRI
0
1
0
RD
RS1
RS2
1
P
W4
O4
15
0
2
5
W4=3, O4=2
15
0
3
Bit Field Extract
RS2
RS1
RD
0
15
0
3
74