
Chapter 12 Serial Peripheral Interface (S12SPIV4)
MC9S12XDP512 Data Sheet, Rev. 2.21
518
Freescale Semiconductor
12.2.3
SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is congured as a master and it is used as an input to receive the slave select
signal when the SPI is congured as slave.
12.2.4
SCK — Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
12.3
Memory Map and Register Denition
This section provides a detailed description of address space and registers used by the SPI.
12.3.1
Module Memory Map
The memory map for the SPI is given in
Figure 12-2. The address listed for each register is the sum of a
base address and an address offset. The base address is dened at the SoC level and the address offset is
dened at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
SPICR1
R
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
W
SPICR2
R
0
MODFEN
BIDIROE
0
SPISWAI
SPC0
W
SPIBR
R
0
SPPR2
SPPR1
SPPR0
0
SPR2
SPR1
SPR0
W
SPISR
R
SPIF
0
SPTEF
MODF
0000
W
Reserved
R
W
SPIDR
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reserved
R
W
Reserved
R
W
= Unimplemented or Reserved
Figure 12-2. SPI Register Summary