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Chapter 7 Debug Module (DBGV1) Block Description
210
MC9S12Q128
Freescale Semiconductor
Rev 1.10
7.3.2.10
Debug Comparator A Register (DBGCA)
PAGSEL
EXTCMP
DBGCXX
0
54321
BIT 0
SEE NOTE 1
PORTK/XAB
XAB21
XAB20
XAB19
XAB18
XAB17
XAB16
XAB15
XAB14
PPAGE
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
SEE NOTE 2
NOTES:
1. In BKP mode, PAGSEL has no functionality. Therefore, set PAGSEL to 00 (reset state).
2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0].
Figure 7-16. Comparators A and B Extended Comparison in BKP Mode
Module Base + 0x002B
Starting address location affected by INITRG register setting.
15
14
13
12
11
10
9
8
R
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
W
Reset
0
00000
Figure 7-17. Debug Comparator A Register High (DBGCAH)
Module Base + 0x002C
Starting address location affected by INITRG register setting.
76543210
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
Reset
0
00000
Figure 7-18. Debug Comparator A Register Low (DBGCAL)
Table 7-21. DBGCA Field Descriptions
Field
Description
15:0
Comparator A Compare Bits — The comparator A compare bits control whether comparator A compares the
address bus bits [15:0] to a logic 1 or logic 0. See
Table 7-20.0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
BKP
MODE