
S12 Clock, Reset and Power Management Unit (S12CPMU)
S12P-Family Reference Manual, Rev. 1.07
Freescale Semiconductor
PRELIMINARY
179
7.3.2.8
S12CPMU RTI Control Register (CPMURTI)
This register selects the timeout period for the Real Time Interrupt.
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 and RTIOSCSEL=1 the RTI continues to run, else the RTI counter halts
in Stop Mode.
Read: Anytime
Write: Anytime
NOTE
A write to this register start or re-starts the RTI time-out period. A change
of the RTIOSCSEL bit (writing a different value or loosing UPOSC status)
re-starts the RTI time-out period.
Table 7-6. CPMUPLL Field Descriptions
Field
Description
5, 4
FM1, FM0
PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This
is to reduce noise emission. The modulation frequency is fref divided by 16. See Table 7-7 for coding. Table 7-7. FM Amplitude selection
FM1
FM0
FM Amplitude /
fVCO Variation
0
FM off
01
±1%
10
±2%
11
±4%
0x003B
76543210
R
RTDEC
RTR6
RTR5
RTR4
RTR3
RTR2
RTR1
RTR0
W
Reset
00000000
Figure 7-11. S12CPMU RTI Control Register (CPMURTI)