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Timer Module (TIM16B8CV2) Block Description
S12P-Family Reference Manual, Rev. 1.12
Freescale Semiconductor
491
14.3.2.18 Output Compare Pin Disconnect Register(OCPD)
Read: Anytime
Write: Anytime
All bits reset to zero.
14.3.2.19 Precision Timer Prescaler Select Register (PTPSR)
Read: Anytime
Write: Anytime
All bits reset to zero.
Module Base + 0x002C
76543210
R
OCPD7
OCPD6
OCPD5
OCPD4
OCPD3
OCPD2
OCPD1
OCPD0
W
Reset
00000000
Figure 14-28. Ouput Compare Pin Disconnect Register (OCPD)
Table 14-21. OCPD Field Description
Field
Description
OCPD[7:0}
Output Compare Pin Disconnect Bits
0 Enables the timer channel port. Ouptut Compare action will occur on the channel pin. These bits do not affect
the input capture or pulse accumulator functions
1 Disables the timer channel port. Output Compare action will not occur on the channel pin, but the output
compare ag still become set .
Module Base + 0x002E
76543210
R
PTPS7
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
PTPS1
PTPS0
W
Reset
00000000
Figure 14-29. Precision Timer Prescaler Select Register (PTPSR)