參數(shù)資料
型號: MC9S12H256VPV
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP112
封裝: LQFP-112
文件頁數(shù): 113/131頁
文件大?。?/td> 2133K
代理商: MC9S12H256VPV
MC9S12H256 Device User Guide — V01.16
82
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
Every supply pair must be decoupled by a ceramic/tantalum capacitor connected as near as possible
to the corresponding pins(C1 – C9).
Central point of the ground star should be the VSS1 pin.
Use low ohmic low inductance connections between VSS1, VSS2, VSSA, VSSX1,2 and
VSSM1,2,3.
VSSPLL must be directly connected to VSS1.
Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C10,
C11, C14 and Q1 as small as possible.
Do not place other signals or supplies underneath area occupied by C10, C11, C14 and Q1 and the
connection area to the MCU.
Central power input should be fed in at the VDDA/VSSA pins.
Table 21-1 Recommended Components
Component
Purpose
Type
Value
C1
VDD1 lter cap
ceramic X7R
100 .. 220nF
C2
VDDA lter cap
X7R/tantalum
>=100nF
C3
VDDX2 lter cap
X7R/tantalum
>=100nF
C4
VDDR lter cap
X7R/tantalum
>=100nF
C5
VDDM3 lter cap
X7R/tantalum
>=100nF
C6
VDDM2 lter cap
X7R/tantalum
>=100nF
C7
VDDM1 lter cap
X7R/tantalum
>=100nF
C8
VDDX1 lter cap
X7R/tantalum
>=100nF
C9
VDDPLL lter cap
ceramic X7R
100nF .. 220nF
C10
OSC load cap
See CRG Block User Guide
C11
OSC load cap
C12
PLL loop lter cap
C13
PLL loop lter cap
C14
DC cutoff cap
R1
PLL loop lter res
Q1
Quartz/Resonator
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