參數(shù)資料
型號: MC9S12H256VFVR2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP144
封裝: LQFP-144
文件頁數(shù): 44/131頁
文件大小: 2133K
代理商: MC9S12H256VFVR2
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
DOCUMENT NUMBER
9S12H256BDGV1/D
2
Revision History
Version
Number
Revision
Date
Effective
Date
Author
Description of Changes
V01.00
07 MAR
2001
03 APR
2001
Initial version.
V01.01
10 MAI
2001
10 MAY
2001
- Minor formal corrections
- Changed ATD coupling ratio to10-2
- Changed VDD5 to 4.5V
V01.02
14 MAY
2001
14 MAY
2001
- Removed 112-pin package references
- Changed ATD Electrical Characteristics separate coupling ratio for
positive and negative bulk current injection
V01.03
30 MAY
2001
30 MAY
2001
- Reinserted 112-pin package information.
V01.04
11 JUN
2001
11 JUN
2001
- Removed SRSv2 comment from preface
- Corrected RESET pin to active low in table 2-1
V01.05
18 JUN
2001
18 JUN
2001
- Adapted style and wording to 9DP256 device user guide
- Minor format and wording improvements
- Added SRAM data retention disclaimer
V01.06
28 JUN
2001
28 JUN
2001
- Changed Oscillator Characteristics tCQOUT max 2.5s and replaced
Clock Monitor Time-out by Clock Monitor Failure Assert Frequency
- Changed Self Clock Mode Frequency min 1MHz and max 5.5MHz
- Changed IDDPS (RTI and COP disabled) to 400A
- Corrected typo in Figure 2-1 pin 76: PK3 -> PK2
V01.07
12 JUL
2001
12 JUL
2001
- Added tEXTR and tEXTF to Oscillator Characteristics
- Added typ value for tUPOSC
- Corrected tEXTL and tEXTH values
- Updated thermal resistances as per Thermal Simulation Report,
July 10, 2001
V01.08
16 JUL
2001
16 JUL
2001
- updated EEPROM size
- added DC cutoff capacitor into layout proposals
V01.09
03 AUG
2001
03 AUG
2001
- minor updates
V01.10
29 AUG
2001
29 AUG
2001
- updated electrical spec
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