參數(shù)資料
型號： MC9S12H256VFVR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP144
封裝： LQFP-144
文件頁數(shù)： 4/131頁
文件大小： 2133K
代理商： MC9S12H256VFVR2
MC9S12H256 Device User Guide — V01.16
101
A.4 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.4.1 Startup
Table A-13 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
A.4.1.1 POR
The release level VPORR and the assert level VPORA are derived from the VDD supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by nuposc.
A.4.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.4.1.3 External Reset
When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
Table A-13 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
T POR release level
VPORR
2.07
V
2
T POR assert level
VPORA
0.97
V
3
D Reset input pulse width, minimum input time
PWRSTL
2
tosc
4
D Startup from Reset
nRST
192
196
nosc
5
D Interrupt pulse width, IRQ edge-sensitive mode
PWIRQ
20
ns
6
D Wait recovery startup time
tWRS
14
tcyc
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MC9S12H256VPV 制造商:Rochester Electronics LLC 功能描述:- Bulk
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