參數(shù)資料
型號(hào): MC9S12DP512MPV
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP112
封裝: LQFP-112
文件頁數(shù): 11/124頁
文件大小: 1963K
代理商: MC9S12DP512MPV
MC9S12DP512 Device Guide V01.21
108
The phase detector relationship is given by:
ich is the current in tracking mode.
The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50.
ζ = 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
fC=10kHz:
The capacitance Cs can now be calculated as:
The capacitance Cp should be chosen in the range of:
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the
deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
KΦ
i
ch
K
V
=
= 316.7Hz/
f
C
2
ζ f
ref
πζ
1
ζ
2
+
------------------------------------------
1
10
------
f
C
f
ref
410
--------------
ζ 0.9
=
()
;
<
<
fC < 25kHz
n
f
VCO
f
ref
-------------
2
synr
1
+
()
==
= 50
R
2
π nf
C
KΦ
-----------------------------
=
=2*
π*50*10kHz/(316.7Hz/)=9.9k=~10k
C
s
2
ζ
2
π f
C R
----------------------
0.516
f
C R
---------------
ζ 0.9
=
()
;
=
= 5.19nF =~ 4.7nF
C
s 20
C
p
C
s 10
≤≤
Cp = 470pF
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