Device User Guide — 9S12DT128DGV2/D V02.15
131
Freescale Semiconductor
A.7.2 Slave Mode
Figure A-8 SPI Slave Timing (CPHA = 0)
Figure A-9 SPI Slave Timing (CPHA =1)
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
SS
(INPUT)
1
9
5
6
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT
SLAVE LSB OUT
BIT 6 . . . 1
10
4
2
7
(CPOL
= 0)
(CPOL
= 1)
3
12
SLAVE
12
11
10
11
8
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
1
5
6
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT
SLAVE LSB OUT
BIT 6 . . . 1
4
9
11
12
10
(CPOL
= 0)
(CPOL
= 1)
SS
(INPUT)
2
12
11
3
SLAVE
7
8
