參數(shù)資料
型號(hào): MC9S12DG128BCPV
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP112
封裝: LQFP-112
文件頁數(shù): 79/128頁
文件大小: 2183K
代理商: MC9S12DG128BCPV
MC9S12DT128B Device User Guide — V01.09
2.2 Signal Properties Summary
Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin
package.
Table 2-1 Signal Properties
Pin Name
Function 1
Pin Name
Function 2
Pin Name
Function 3
Pin Name
Function 4
Pin Name
Function 5
Powered
by
Internal Pull
Resistor
Description
CTRL
Reset
State
EXTAL
————
VDDPLL
NA
Oscillator Pins
XTAL
————
VDDPLL
NA
RESET
————
VDDR
None
External Reset
TEST
————
N.A.
None
Test Input
VREGEN
————
VDDX
NA
Voltage Regulator
Enable Input
XFC
————
VDDPLL
NA
PLL Loop Filter
BKGD
TAGHI
MODC
VDDR
Always
Up
Background Debug,
Tag High, Mode Input
PAD[15]
AN1[7]
ETRIG1
VDDA
None
Port AD Input,
Analog Inputs,
External Trigger
Input (ATD1)
PAD[14:8]
AN1[6:0]
VDDA
None
Port AD Input,
Analog Inputs
(ATD1)
PAD[7]
AN0[7]
ETRIG0
VDDA
None
Port AD Input, Analog
Inputs, External
Trigger Input (ATD0)
PAD[6:0]
AN0[6:0]
VDDA
None
Port AD Input, Analog
Inputs (ATD0)
PA[7:0]
ADDR[15:8]/
DATA[15:8]
VDDR
PUCR/
PUPAE
Disabled
Port A I/O,
Multiplexed
Address/Data
PB[7:0]
ADDR[7:0]/
DATA[7:0]
VDDR
PUCR/
PUPBE
Disabled
Port B I/O,
Multiplexed
Address/Data
PE7
NOACC
XCLKS
VDDR
PUCR/
PUPEE
Up
Port E I/O, Access,
Clock Select
PE6
IPIPE1
MODB
VDDR
While RESET pin
low:
Down
Port E I/O, Pipe
Status, Mode Input
PE5
IPIPE0
MODA
VDDR
Port E I/O, Pipe
Status, Mode Input
PE4
ECLK
VDDR
PUCR/
PUPEE
Up
Port E I/O, Bus Clock
Output
PE3
LSTRB
TAGLO
VDDR
PUCR/
PUPEE
Up
Port E I/O, Byte
Strobe, Tag Low
PE2
R/W
VDDR
PUCR/
PUPEE
Up
Port E I/O, R/W in
expanded modes
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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