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參數(shù)資料
| 型號： | MC9S12DB128VPVE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 128K FLASH 25MHZ 112-LFP |
| 標(biāo)準(zhǔn)包裝： | 300 |
| 系列： | HCS12 |
| 核心處理器： | HCS12 |
| 芯體尺寸： | 16-位 |
| 速度： | 25MHz |
| 連通性： | CAN，I²C，SCI，SPI |
| 外圍設(shè)備： | PWM，WDT |
| 輸入/輸出數(shù)： | 91 |
| 程序存儲器容量： | 128KB（128K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 2K x 8 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.35 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 112-LQFP |
| 包裝： | 托盤 |
MC9S
2
PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
Analog-to-Digital Converters
— One or two 8-channel modules with 10-bit resolution depending on the package option
— External conversion trigger capability
Up to five 1M bit per second, CAN 2.0 A, B software compatible modules
— Five receive and three transmit buffers
— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
— Four separate interrupt channels for Receive, Transmit, Error and Wake-up
— Low-pass filter wake-up function in STOP mode
— Loop-back for self test operation
Enhanced Capture Timer (ECT)
— 16-bit main counter with 7-bit prescaler
— 8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer
— Input capture filters and buffers, three successive captures on four channels, or two captures on four
channels with a capture/compare selectable on the remaining four
— Four 8-bit or two 16-bit pulse accumulators
— 16-bit modulus down-counter with 4-bit prescaler
— Four user-selectable delay counters for signal filtering
8 PWM channels with programmable period and duty cycle (7 channels on 80 Pin Packages)
— 8-bit, 8-channel or 16-bit, 4-channel
— Separate control for each pulse width and duty cycle
— Center- or left-aligned outputs
— Programmable clock select logic with a wide range of frequencies
Serial interfaces
— Two asynchronous serial communications interfaces (SCI)
— Up to three synchronous serial peripheral interfaces (SPI)
— IIC
SAE J1850 Compatible Module (BDLC)
— 10.4 kbps Variable Pulse Width format
— Byte level receive and transmit
— 4x receive mode supported
SIM (System Integration Module)
— CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and reset)
— MEBI (multiplexed external bus interface)
— INT (interrupt control)
Clock generation
— Phase-locked loop clock frequency multiplier
— Limp home mode in absence of external clock
— Clock Monitor
— Low power 0.5 to 16 MHz crystal oscillator reference clock
Operating frequency for ambient temperatures TA -40°C <= TA <= 125°C
— 50MHz equivalent to 25MHz Bus Speed for single chip
40MHz equivalent to 20MHz Bus Speed in expanded bus modes.
Internal 5V to 2.5V Regulator
112-Pin LQFP or 80-Pin QFP package
— I/O lines with 5V input and drive capability
— 5V A/D converter inputs and 5V I/O
— 2.5V logic supply
Development support
— Single-wire background debug mode (BDM)
— On-chip hardware breakpoints
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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