
Device User Guide — 9S12C128DGV1/D V01.07
120
Figure C-2 SPI Master Timing (CPHA=1)
In Table C-2 the timing characteristics for master mode are listed.
Table C-2 SPI Master Mode Timing Characteristics
Num
C
Characteristic
Symbol
Unit
Min
Typ
Max
1
P
SCK Frequency
fsck
1/2048
—
1
/2
fbus
1
P
SCK Period
tsck
2
—
2048
tbus
2
D
Enable Lead Time
tlead
—
1/2
—
tsck
3
D
Enable Lag Time
tlag
—
1/2
—
tsck
4
D
Clock (SCK) High or Low Time
twsck
—
1/2
—
tsck
5
D
Data Setup Time (Inputs)
tsu
8—
—
ns
6
D
Data Hold Time (Inputs)
thi
8—
—
ns
9
D
Data Valid after SCK Edge
tvsck
—
30
ns
10
D
Data Valid after SS fall (CPHA=0)
tvss
—
15
ns
11
D
Data Hold Time (Outputs)
tho
20
—
ns
12
D
Rise and Fall Time Inputs
tr
——
8
ns
13
D
Rise and Fall Time Outputs
trfo
——
8
ns
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
1
5
6
MSB IN2
BIT 6 . . . 1
LSB IN
MASTER MSB OUT2
MASTER LSB OUT
BIT 6 . . . 1
4
9
12
13
11
PORT DATA
(CPOL
= 0)
(CPOL
= 1)
PORT DATA
SS1
(OUTPUT)
2
12
13
3
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
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