參數資料
    

    


    


    
型號：
MC9S12C64PCPB25

    

    
廠商：
MOTOROLA INC

    

    
元件分類：
微控制器/微處理器

    

    
英文描述：
16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP52

    

    
封裝：
LQFP-52

    

    
文件頁數：
95/136頁

    

    
文件大小：
2022K

    

    
代理商：
MC9S12C64PCPB25


    

    

    

	
    
    
    

    
    
	
    Device User Guide — 9S12C128DGV1/D V01.05
    61
    2.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt Pin
    The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling
    edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is
    always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing
    IRQEN bit (INTCR register). When the MCU is reset the IRQ function is masked in the condition code
    register. This pin is always an input and can always be read. There is an active pull-up on this pin while in
    reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.
    2.3.15 PE0 / XIRQ — Port E input Pin [0] / Non Maskable Interrupt Pin
    The XIRQ input provides a means of requesting a non maskable interrupt after reset initialization. During
    reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software
    enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR
    network. This pin is always an input and can always be read. There is an active pull-up on this pin while
    in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR
    register.
    2.3.16 PAD[7:0] / AN[7:0] — Port AD I/O Pins [7:0]
    PAD7-PAD0 are general purpose I/O pins and also analog inputs for the analog to digital converter. In
    order to use a PAD pin as a standard I/O, the corresponding ATDDIEN register bit must be set. These bits
    are cleared out of reset to configure the PAD pins for A/D operation.
    When the A/D converter is active in multi-channel mode, port inputs are scanned and converted
    irrespective of PortAD configuration. Thus PortAD pins that are configured as digital inputs or digital
    outputs are also converted in the A/D conversion sequence.
    2.3.17 PP[7] / KWP[7] — Port P I/O Pin [7]
    PP7 is a general purpose input or output pin, shared with the keypad interrupt function. When configured
    as an input, it can generate interrupts causing the MCU to exit STOP or WAIT mode. This pin is not
    available in the 48 / 52 pin package versions.
    2.3.18 PP[6] / KWP[6]/ROMCTL — Port P I/O Pin [6]
    PP6 is a general purpose input or output pin, shared with the keypad interrupt function. When configured
    as an input, it can generate interrupts causing the MCU to exit STOP or WAIT mode. This pin is not
    available in the 48 / 52 pin package versions. During MCU expanded modes of operation, this pin is used
    to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the
    state of this pin is latched to the ROMON bit.
    PP6=1 in emulation modes equates to ROMON =0
    (ROM space externally mapped)
    PP6=0 in expanded modes equates to ROMON =0 (ROM space externally mapped)
    
    
    
    
    
    


    


    

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MC9S12C64VFAE
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MC9S12C96CFAE
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