參數(shù)資料
型號: MC9S12B64VPV25
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP112
封裝: LQFP-112
文件頁數(shù): 81/132頁
文件大?。?/td> 1842K
代理商: MC9S12B64VPV25
Device User Guide — 9S12B128DGV1/D V01.13
52
2.1.1 Signal Properties Summary
Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin
package.
Table 2-1 Signal Properties
Pin Name
Function1
Pin Name
Function2
Pin Name
Function
3
Pin Name
Function
4
Powered
by
Internal Pull
Resistor
Description
CTRL
Reset
State
EXTAL
VDDPLL
None
Oscillator Pins
XTAL
RESET
VDDR
External Reset
TEST
N.A.
Test Input
VREGEN
VDDX
Voltage Regulator Enable Input
XFC
VDDPLL
PLL Loop Filter
BKGD
TAGHI
MODC
VDDR
Always
Up
Background Debug, Tag High, Mode
Input
PAD[15:8]
AN[15:8]
VDDA
None
Port AD Inputs, Analog Inputs
AN[15:8] of ATD
PAD[07:00]
AN[07:00]
Port AD Inputs, Analog Inputs
AN[7:0] of ATD
PA[7:0]
ADDR[15:8]/
DATA[15:8]
——
VDDR
PUCR/
PUPAE
Disabled
Port A I/O, Multiplexed Address/Data
PB[7:0]
ADDR[7:0]/
DATA[7:0]
——
PUCR/
PUPBE
Port B I/O, Multiplexed Address/Data
PE7
NOACC
XCLKS
PUCR/
PUPEE
Up
Port E I/O, Access, Clock Select
PE6
IPIPE1
MODB
While RESET pin
is low:
Down
Port E I/O, Pipe Status, Mode Input
PE5
IPIPE0
MODA
Port E I/O, Pipe Status, Mode Input
PE4
ECLK
PUCR/
PUPEE
Mode
depende
nt1
Port E I/O, Bus Clock Output
PE3
LSTRB
TAGLO
Port E I/O, Byte Strobe, Tag Low
PE2
R/W
Port E I/O, R/W in expanded modes
PE1
IRQ
Up
Port E Input, Maskable Interrupt
PE0
XIRQ
Port E Input, Non Maskable Interrupt
PH7
KWH7
——
PERH/
PPSH
Disabled
Port H I/O, Interrupt
PH6
KWH6
——
Port H I/O, Interrupt
PH5
KWH5
——
Port H I/O, Interrupt
PH4
KWH4
——
Port H I/O, Interrupt
PH3
KWH3
——
Port H I/O, Interrupt
PH2
KWH2
——
Port H I/O, Interrupt
PH1
KWH1
——
Port H I/O, Interrupt
PH0
KWH0
——
Port H I/O, Interrupt
PJ7
KWJ7
SCL
VDDX
PERJ/
PPSJ
Up
Port J I/O, Interrupt, SCL of IIC,
PJ6
KWJ6
SDA
Port J I/O, Interrupt, SDA of IIC,
PJ[1:0]
KWJ[1:0]
Port J I/O, Interrupts
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