參數(shù)資料
型號: MC9S12A256
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16 bit Microcontroller Unit (MCU)(16位MCU)
中文描述: 16位微控制器單元(MCU)(16位微控制器)
文件頁數(shù): 54/132頁
文件大?。?/td> 782K
代理商: MC9S12A256
MC9S12DT256 Device User Guide — V03.07
54
Pin Name
Funct. 1
Pin Name
Funct. 2
Pin Name
Funct. 3
Pin Name
Funct. 4
Pin Name
Funct. 5
Power
Supply
Internal Pull
Resistor
Description
CTRL
Reset
State
NA
NA
EXTAL
XTAL
VDDPLL
VDDPLL
NA
NA
Oscillator Pins
RESET
VDDR
None
None
External Reset
TEST
N.A.
NA
NA
Test Input
VREGEN
VDDX
NA
NA
Voltage Regulator Enable Input
XFC
VDDPLL
NA
NA
PLL Loop Filter
BKGD
TAGHI
MODC
VDDR
Always
Up
Up
Background Debug, Tag High, Mode
Input
Port AD Input, Analog Input AN7
of ATD1, External Trigger Input of
ATD1
Port AD Inputs, Analog Inputs
AN[6:0] of ATD1
PAD[15]
AN1[7]
ETRIG1
VDDA
None
None
PAD[14:8]
AN1[6:0]
VDDA
None
None
PAD[7]
AN0[7]
ETRIG0
VDDA
None
None
Port AD Input, Analog Input AN7 of
ATD0, External Trigger Input of ATD0
PAD[6:0]
AN0[6:0]
VDDA
None
None
Port AD Inputs, Analog Inputs
AN[6:0] of ATD0
PA[7:0]
ADDR[15:8]/
DATA[15:8]
ADDR[7:0]/
DATA[7:0]
VDDR
PUCR
Disabled
Port A I/O, Multiplexed Address/Data
PB[7:0]
VDDR
PUCR
Disabled
Port B I/O, Multiplexed Address/Data
PE7
NOACC
XCLKS
VDDR
PUCR
Up
Port E I/O, Access, Clock Select
PE6
IPIPE1
MODB
VDDR
While RESET
pin is low:
Down
Port E I/O, Pipe Status, Mode Input
PE5
IPIPE0
MODA
VDDR
While RESET
pin is low:
Down
Port E I/O, Pipe Status, Mode Input
PE4
ECLK
VDDR
PUCR
Up
Port E I/O, Bus Clock Output
PE3
LSTRB
TAGLO
VDDR
PUCR
Up
Port E I/O, Byte Strobe, Tag Low
PE2
R/W
VDDR
PUCR
Up
Port E I/O, R/W in expanded modes
PE1
IRQ
VDDR
PUCR
Up
Port E Input, Maskable Interrupt
PE0
XIRQ
VDDR
PUCR
Up
Port E Input, Non Maskable Interrupt
PH7
KWH7
SS2
VDDR
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
Disabled
Port H I/O, Interrupt, SS of SPI2
PH6
KWH6
SCK2
VDDR
Disabled
Port H I/O, Interrupt, SCK of SPI2
PH5
KWH5
MOSI2
VDDR
Disabled
Port H I/O, Interrupt, MOSI of SPI2
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