參數(shù)資料
型號(hào): MC9S12A128BCFU
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 46/92頁
文件大小: 1229K
代理商: MC9S12A128BCFU
MC9S12A128 Device Guide — V01.01
50
5.3 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states.
5.3.1 I/O Pins
Refer to the HCS12 Core User Guide (Motorola document order number HCS12COREUG/D) for mode
dependent pin configuration of port A, B, E and K out of reset.
Refer to the MC9S12A128 Port Integration Module (PIM) Block Guide (Motorola document order
number, S12A128PIMV1/D) for reset configurations of all peripheral module ports.
NOTE:
For devices assembled in 80-pin QFP packages all non-bonded out pins should be
configured as outputs after reset in order to avoid current drawn from floating
inputs. Refer to Table 2-1 Signal Properties for affected pins.
5.3.2 Memory
Refer to Table 1-1 Device Memory Map for locations of the memories depending on the operating
mode after reset.
The RAM array is not automatically initialized out of reset.
$FFC8, $FFC9
Pulse Accumulator B Overflow
I-Bit
PBCTL(PBOVI)
$C8
$FFC6, $FFC7
CRG PLL lock
I-Bit
CRGINT(LOCKIE)
$C6
$FFC4, $FFC5
CRG Self Clock Mode
I-Bit
CRGINT (SCMIE)
$C4
$FFC2, $FFC3
Reserved
$FFC0, $FFC1
IIC Bus
I-Bit
IBCR (IBIE)
$C0
$FFBE, $FFBF
SPI1
I-Bit
SP1CR1 (SPIE, SPTIE)
$BE
$FFBC, $FFBD
Reserved
$FFBA, $FFBB
EEPROM
I-Bit
EECTL(CCIE, CBEIE)
$BA
$FFB8, $FFB9
FLASH
I-Bit
FCTL(CCIE, CBEIE)
$B8
$FF90 to
$FFB7
Reserved
$FF8E, $FF8F
Port P Interrupt
I-Bit
PTPIF (PTPIE)
$8E
$FF8C, $FF8D
PWM Emergency Shutdown
I-Bit
PWMSDN (PWMIE)
$8C
$FF80 to
$FF8B
Reserved
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