
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Freescale Semiconductor
109
SUB #opr8i
SUB opr8a
SUB opr16a
SUB oprx16,X
SUB oprx8,X
SUB ,X
SUB oprx16,SP
SUB oprx8,SP
Subtract
A
← (A) – (M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A0
B0
C0
D0
E0
F0
9E D0
9E E0
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
3
5
4
pp
rpp
prpp
rpp
rfp
pprpp
prpp
11 – –
SWI
Software Interrupt
PC
← (PC) + $0001
Push (PCL); SP
← (SP) – $0001
Push (PCH); SP
← (SP) – $0001
Push (X); SP
← (SP) – $0001
Push (A); SP
← (SP) – $0001
Push (CCR); SP
← (SP) – $0001
I
← 1;
PCH
← Interrupt Vector High Byte
PCL
← Interrupt Vector Low Byte
INH
83
11
sssssvvfppp
–11– 1–––
TAP
Transfer Accumulator to CCR
CCR
← (A)
INH
84
1
p
11
TAX
Transfer Accumulator to X (Index Register
Low)
X
← (A)
INH
97
1
p
–11– ––––
TPA
Transfer CCR to Accumulator
A
← (CCR)
INH
85
1
p
–11– ––––
TST opr8a
TSTA
TSTX
TST oprx8,X
TST ,X
TST oprx8,SP
Test for Negative or Zero
(M) – $00
(A) – $00
(X) – $00
(M) – $00
DIR
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E 6D
dd
ff
4
1
4
3
5
rfpp
p
rfpp
rfp
prfpp
011– –
–
TSX
Transfer SP to Index Reg.
H:X
← (SP) + $0001
INH
95
2
fp
–11– ––––
TXA
Transfer X (Index Reg. Low) to Accumulator
A
← (X)
INH
9F
1
p
–11– ––––
Table 7-2. Instruction Set Summary (Sheet 8 of 9)
Source
Form
Operation
Ad
dress
Mode
Object Code
Cyc
les
Cyc-by-Cyc
Details
Affect
on CCR
V 1 1 H I N Z C