Appendix A Electrical Characteristics
MC9S08SG32 Data Sheet, Rev. 7
306
Freescale Semiconductor
A.9
Internal Clock Source (ICS) Characteristics
Table A-9. ICS Frequency Specications (Temperature Range = –40 to 125
°C Ambient)
#
C
Rating
Symbol
Min
Typical
Max
Unit
Temp Rated
Standar
d
AEC
Grade
0
1P
Internal reference frequency — factory
trimmed at VDD = 5 V and temperature =
25
°C
fint_ft
—
31.25
—
kHz
2T
Internal reference frequency —
untrimmed1
1 TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
fint_ut
25
36
41.66
kHz
3
P Internal reference frequency — trimmed
fint_t
31.25
—
39.0625
kHz
4
D Internal reference startup time
tirefst
—
55
100
μs
5—
DCO output frequency range —
untr
immed1 value provided for reference:
fdco_ut = 1024 x fint_ut
fdco_ut
25.6
36.86
42.66
MHz
6
D DCO output frequency range — trimmed
fdco_t
32
—
40
MHz
—
32
—
36
MHz
—
7D
Resolution of trimmed DCO output
frequency at xed voltage and temperature
(using FTRIM)
Δfdco_res_t
—
± 0.1
± 0.2
%fdco
8D
Resolution of trimmed DCO output
frequency at xed voltage and temperature
(not using FTRIM)
Δfdco_res_t
—
± 0.2
± 0.4
%fdco
9D
Total deviation of trimmed DCO output
frequency over voltage and temperature
Δfdco_t
—
+ 0.5
– 1.0
± 1.5
%fdco
—
—
+ 0.5
– 1.0
± 3
%fdco
—
10
D
Total deviation of trimmed DCO output
frequency over xed voltage and
temperature range of 0
°C to 70 °C
Δfdco_t
—
± 0.5
± 1
%fdco
11
D FLL acquisition time 2
2 This specication applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specication assumes it is already running.
tacquire
—1
ms
12
D
DCO output clock long term jitter (over 2
ms interval) 3
3 Jitter is the average deviation from the programmed frequency measured over the specied interval at maximum f
BUS.
Measurements are made with the device powered by ltered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
CJitter
—
0.02
0.2
%fdco