Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
MC9S08SG32 Data Sheet, Rev. 8
130
Freescale Semiconductor
9.3.1
Status and Control Register 1 (ADCSC1)
This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1
aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other
than all 1s).
7654
3
210
R
COCO
AIEN
ADCO
ADCH
W
Reset:
0
1
= Unimplemented or Reserved
Figure 9-3. Status and Control Register (ADCSC1)
Table 9-3. ADCSC1 Register Field Descriptions
Field
Description
7
COCO
Conversion Complete Flag — The COCO ag is a read-only bit set each time a conversion is completed when
the compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE = 1), the COCO ag
is set upon completion of a conversion only if the compare result is true. This bit is cleared when ADCSC1 is
written or whenever ADCRL is read.
0 Conversion not completed
1 Conversion completed
6
AIEN
Interrupt Enable — AIEN enables conversion complete interrupts. When COCO becomes set while AIEN is
high, an interrupt is asserted.
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled
5
ADCO
Continuous Conversion Enable — ADCO enables continuous conversions.
0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one
conversion following assertion of ADHWT when hardware triggered operation is selected.
1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected.
Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected.
4:0
ADCH
Input Channel Select — The ADCH bits form a 5-bit eld which that selects one of the input channels. The input
The successive approximation converter subsystem is turned off when the channel select bits are all set. This
feature allows for explicit disabling of the ADC and isolation of the input channel from all sources. Terminating
continuous conversions this way prevents an additional, single conversion from being performed. It is not
necessary to set the channel select bits to all ones to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.
Table 9-4. Input Channel Select
ADCH
Input Select
ADCH
Input Select
00000
AD0
10000
AD16
00001
AD1
10001
AD17
00010
AD2
10010
AD18
00011
AD3
10011
AD19