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    參數(shù)資料
    型號(hào): MC9S08SF4CTJ
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: MICROCONTROLLER, PDSO20
    封裝: 0.65 MM PITCH, ROHS COMPLIANT, TSSOP-20
    文件頁(yè)數(shù): 10/32頁(yè)
    文件大小: 564K
    代理商: MC9S08SF4CTJ
    MC9S08SF4 Series MCU Data Sheet, Rev. 2
    AC Characteristics
    Freescale Semiconductor
    18
    3.9.1
    Control Timing
    Figure 14. Reset Timing
    Figure 15. IRQ/KBIPx Timing
    Table 9. Control Timing
    Parameter
    Symbol
    Min
    Typical1
    1 Data in Typical column was characterized at 5.0 V, 25
    °C.
    Max
    Unit
    Bus frequency (tcyc = 1/fBus)fBus
    1—
    20
    MHz
    External reset pulse width2
    2 This is the shortest pulse that is guaranteed to be recognized.
    textrst
    100
    ns
    IRQ pulse width
    Asynchronous path2
    Synchronous path3
    3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
    may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
    tILIH, tIHIL
    100
    1.5 tcyc
    ——
    ns
    KBIPx pulse width
    Asynchronous path2
    Synchronous path3
    tILIH, tIHIL
    100
    1.5 tcyc
    ——
    ns
    Port rise and fall time (load = 50 pF)4
    Slew rate control disabled (PTxSE = 0)
    Slew rate control enabled (PTxSE = 1)
    4 Timing is shown with respect to 20% V
    DD and 80% VDD levels. Temperature range –40°C to 125°C.
    tRise, tFall
    3
    30
    ns
    BKGD/MS setup time after issuing background debug force
    reset to enter user or BDM modes
    tMSSU
    500
    ns
    BKGD/MS hold time after issuing background debug force
    reset to enter user or BDM modes 5
    5 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
    MSH after VDD
    rises above VLVD.
    tMSH
    100
    μs
    textrst
    RESET PIN
    tIHIL
    IRQ/KBIPx
    tILIH
    IRQ/KBIPx
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