參數(shù)資料
型號(hào): MC9S08RG32FG
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 1.40 MM THICKNESS, 0.80 MM PITCH, MS-026BCB, LQFP-44
文件頁數(shù): 69/234頁
文件大?。?/td> 1743K
代理商: MC9S08RG32FG
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Serial Communications Interface (S08SCIV1)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
160
Freescale Semiconductor
12.3.3.2.1
Idle-Line Wakeup
When WAKE = 0, the receiver is congured for idle-line wakeup. In this mode, RWU is cleared
automatically when the receiver detects a full character time of the idle-line level. The M control bit selects
8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character
time (10 or 11 bit times because of the start and stop bits). The idle-line type (ILT) control bit selects one
of two ways to detect an idle line:
When ILT = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end
of a character count toward the full character time of idle.
When ILT = 1, the idle bit counter doesn’t start until after a stop bit time, so the idle detection is
not affected by the data in the last character of the previous message.
12.3.3.2.2
Address-Mark Wakeup
When WAKE = 1, the receiver is congured for address-mark wakeup. In this mode, RWU is cleared
automatically when the receiver detects a logic 1 in the most signicant bit of a received character (eighth
bit in M = 0 mode and ninth bit in M = 1 mode).
12.3.4
Interrupts and Status Flags
The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the
cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events.
Another interrupt vector is associated with the receiver for RDRF and IDLE events, and a third vector is
used for OR, NF, FE, and PF error conditions. Each of these eight interrupt sources can be separately
masked by local interrupt enable masks. The ags can still be polled by software when the local masks are
cleared to disable generation of hardware interrupt requests.
The SCI transmitter has two status ags that optionally can generate hardware interrupt requests. Transmit
data register empty (TDRE) indicates when there is room in the transmit data buffer to write another
transmit character to SCI1D. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be
requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is nished
transmitting all data, preamble, and break characters and is idle with TxD1 high. This ag is often used in
systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt
enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. Instead of hardware
interrupts, software polling may be used to monitor the TDRE and TC status ags if the corresponding TIE
or TCIE local interrupt masks are 0s.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCI1D. The RDRF ag is cleared by reading SCI1S1 while RDRF = 1 and then
reading SCI1D.
When polling is used, this sequence is naturally satised in the normal course of the user program. If
hardware interrupts are used, SCI1S1 must be read in the interrupt service routine (ISR). Normally, this is
done in the ISR anyway to check for receive errors, so the sequence is automatically satised.
The IDLE status ag includes logic that prevents it from getting set repeatedly when the RxD1 line remains
idle for an extended period of time. IDLE is cleared by reading SCI1S1 while IDLE = 1 and then reading
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