
Memory
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
50
Freescale Semiconductor
if PRDIV8 = 0 — fFCLK = fBus ÷ ([DIV5:DIV0] + 1)
Eqn. 4-1
if PRDIV8 = 1 — fFCLK = fBus ÷ (8 × ([DIV5:DIV0] + 1))
Eqn. 4-2
Table 4-6 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.
76543210
R
DIVLD
PRDIV8
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
W
Reset
00000000
= Unimplemented or Reserved
Figure 4-5. FLASH Clock Divider Register (FCDIV)
Table 4-5. FCDIV Field Descriptions
Field
Description
7
DIVLD
Divisor Loaded Status Flag — When set, this read-only status ag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the rst write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
6
PRDIV8
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
5:0
DIV[5:0]
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 eld plus one. The resulting frequency of the
internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations.
Program/erase timing pulses are one cycle of this internal FLASH clock, which corresponds to a range of 5
s
to 6.7
s. The automated programming logic uses an integer number of these pulses to complete an erase or
Table 4-6. FLASH Clock Divider Settings
fBus
PRDIV8
(Binary)
DIV5:DIV0
(Decimal)
fFCLK
Program/Erase Timing Pulse
(5
s Min, 6.7 s Max)
8 MHz
0
39
200 kHz
5
s
4 MHz
0
19
200 kHz
5
s
2 MHz
0
9
200 kHz
5
s
1 MHz
0
4
200 kHz
5
s
200 kHz
0
200 kHz
5
s
150 kHz
0
150 kHz
6.7
s