Electrical Characteristics
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
215
Table A-11. SPI Electrical Characteristic
Number(1)
Characteristic(2)
2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all
SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI
output pins.
Symbol
Min
Max
Unit
Operating frequency(3)
Master
Slave
3. Maximum baud rate must be limited to 5 MHz due to pad input characteristics.
fop
fBus/2048
dc
fBus/2
fBus/4
Hz
1
Cycle time
Master
Slave
tSCK
2
4
2048
—
tcyc
2
Enable lead time
Master
Slave
tLead
—
1/2
—
tSCK
3
Enable lag time
Master
Slave
tLag
—
1/2
—
tSCK
4
Clock (SPSCK) high time
Master and Slave
tSCKH
1/2 tSCK – 25
—
ns
5
Clock (SPSCK) low time
Master and Slave
tSCKL
1/2 tSCK – 25
—
ns
6
Data setup time (inputs)
Master
Slave
tSI(M)
tSI(S)
30
—
ns
7
Data hold time (inputs)
Master
Slave
tHI(M)
tHI(S)
30
—
ns
8
Access time, slave(4)
4. Time to data active from high-impedance state.
tA
040
ns
9
Disable time, slave(5)
5. Hold time to high-impedance state.
tdis
—40
ns
10
Data setup time (outputs)
Master
Slave
tSO
25
—
ns
11
Data hold time (outputs)
Master
Slave
tHO
–10
—
ns