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| 型號(hào)： | MC9S08RC16CFJ |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32 |
| 文件頁數(shù)： | 105/234頁 |
| 文件大小： | 1743K |
| 代理商： | MC9S08RC16CFJ |
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Development Support
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
193
the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the rst signicant entry
in the FIFO.
In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-ow addresses. In
these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading
DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information
is available at the FIFO data port. In the event-only trigger modes (see Section 15.3.5, “Trigger Modes”),
8-bit data information is stored into the FIFO. In these cases, the high-order half of the FIFO (DBGFH) is
not used and data is read out of the FIFO by simply reading DBGFL. Each time DBGFL is read, the FIFO
is shifted so the next data value is available through the FIFO data port at DBGFL.
In trigger modes where the FIFO is storing change-of-ow addresses, there is a delay between CPU
addresses and the input side of the FIFO. Because of this delay, if the trigger event itself is a change-of-ow
address or a change-of-ow address appears during the next two bus cycles after a trigger event starts the
FIFO, it will not be saved into the FIFO. In the case of an end-trace, if the trigger event is a change-of-ow,
it will be saved as the last change-of-ow entry for that debug run.
The FIFO can also be used to generate a prole of executed instruction addresses when the debugger is not
armed. When ARM = 0, reading DBGFL causes the address of the most-recently fetched opcode to be
saved in the FIFO. To use the proling feature, a host debugger would read addresses out of the FIFO by
reading DBGFH then DBGFL at regular periodic intervals. The rst eight values would be discarded
because they correspond to the eight DBGFL reads needed to initially ll the FIFO. Additional periodic
reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger
can develop a prole of executed instruction addresses.
15.3.3
Change-of-Flow Information
To minimize the amount of information stored in the FIFO, only information related to instructions that
cause a change to the normal sequential execution of instructions is stored. With knowledge of the source
and object code program stored in the target system, an external debugger system can reconstruct the path
of execution through many instructions from the change-of-ow information stored in the FIFO.
For conditional branch instructions where the branch is taken (branch condition was true), the source
address is stored (the address of the conditional branch opcode). Because BRA and BRN instructions are
not conditional, these events do not cause change-of-ow information to be stored in the FIFO.
Indirect JMP and JSR instructions use the current contents of the H:X index register pair to determine the
destination address, so the debug system stores the run-time destination address for any indirect JMP or
JSR. For interrupts, RTI, or RTS, the destination address is stored in the FIFO as change-of-ow
information.
15.3.4
Tag vs. Force Breakpoints and Triggers
Tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue,
but not taking any other action until and unless that instruction is actually executed by the CPU. This
distinction is important because any change-of-ow from a jump, branch, subroutine call, or interrupt
causes some instructions that have been fetched into the instruction queue to be thrown away without being
executed.
相關(guān)PDF資料 |
PDF描述 |
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| MC9S08RD16FJ | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 |
| MC9S08RG32FG | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| MC9S08RE16FD | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC48 |
| MC9S08RC8FG | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| MC9S08RE16FJ | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9S08RC16CFJE | 功能描述:IC MCU 16K FLASH 8MHZ 32-LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:S08 標(biāo)準(zhǔn)包裝:1 系列:87C 核心處理器:MCS 51 芯體尺寸:8-位 速度:16MHz 連通性:SIO 外圍設(shè)備:- 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:8KB（8K x 8） 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4 V ~ 6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:外部 工作溫度:0°C ~ 70°C 封裝/外殼:44-DIP 包裝:管件 其它名稱:864285 |
| MC9S08RC16CPE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08RC16DWE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08RC16FDE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08RC16FG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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