參數資料
型號: MC9S08QE4CWJ
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO20
封裝: 1.27 MM PITCH, ROHS COMPLIANT, MS-013AC, SOIC-28
文件頁數: 2/46頁
文件大?。?/td> 1293K
代理商: MC9S08QE4CWJ
MC9S08QE8 Series Data Sheet, Rev. 7
Electrical Characteristics
Freescale Semiconductor
10
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification, ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 5. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
Human
Body
Series resistance
R1
1500
Ω
Storage capacitance
C
100
pF
Number of pulses per pin
3
Machine
Series resistance
R1
0
Ω
Storage capacitance
C
200
pF
Number of pulses per pin
3
Latch-up
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
Table 6. ESD and Latch-Up Protection Characteristics
No.
Rating1
1 Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
±2000
V
2
Machine model (MM)
VMM
±200
V
3
Charge device model (CDM)
VCDM
±500
V
4
Latch-up current at TA = 85 °CILAT
±100
mA
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