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| 型號(hào)： | MC9S08QD2VPC |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PDIP8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 156/198頁(yè) |
| 文件大小： | 2473K |
| 代理商： | MC9S08QD2VPC |
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Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 6
60
Freescale Semiconductor
5.8.3
System Background Debug Force Reset Register (SBDFR)
This high-page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
5
COP
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source can be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
4
ILOP
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
3
ILAD
Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented
memory address.
0 Reset not caused by an illegal address
1 Reset caused by an illegal address
1
LVD
Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will
occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
76
54
321
0
R
000
00
000
W
BDFR1
Reset:
000
00
000
= Unimplemented or Reserved
1 BDFR is writable only through serial background debug commands, not from user programs.
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
Table 5-5. SBDFR Register Field Descriptions
Field
Description
0
BDFR
Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program. To enter user mode, PTA4/TPM2CH0O/BKGD/MS must be high immediately
after issuing WRITE_BYTE command. To enter BDM, PTA4/TPM2CH0O/BKGD/MS must be low immediately
after issuing WRITE_BYTE command. See A.8.1, “Control Timing,” for more information.
Table 5-4. SRS Register Field Descriptions (continued)
Field
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC9S08QE128CQD | 8-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP44 |
| MC9S08QE128CLC | 8-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP32 |
| MC9S08QE64CQD | 8-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP44 |
| MC9S08QE96CLH | 8-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP64 |
| MC9S08QE128CFT | 8-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, QCC48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9S08QD2VPS | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit HCS08 Central Processor Unit (CPU) |
| MC9S08QD2VSC | 功能描述:8位微控制器 -MCU 9S08QD4 SERIES RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC9S08QD2VSCR | 制造商:Freescale Semiconductor 功能描述:9S08QD4 SERIES - Tape and Reel |
| MC9S08QD4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08QD4_07 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit HCS08 Central Processor Unit (CPU) |
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