參數(shù)資料
型號(hào): MC9S08LG32CLF
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 22/50頁(yè)
文件大?。?/td> 0K
描述: IC MCU 8BIT LG32 FLASH 48-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: S08
核心處理器: S08
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SCI,SPI
外圍設(shè)備: LCD,LVD,PWM
輸入/輸出數(shù): 39
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1.9K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-LQFP
包裝: 托盤
配用: DEMO9S08LG32-ND - DEMO BOARD FOR LG32 FAMILY MCU
Electrical Characteristics
MC9S08LG32 Series Data Sheet, Rev. 9
Freescale Semiconductor
29
2.11
AC Characteristics
This section describes timing characteristics for each peripheral system.
2.11.1
Control Timing
Figure 19. Reset Timing
Table 14. Control Timing
Num
C
Rating
Symbol
Min
Typ1
1 Typical values are based on characterization data at V
DD = 5.0 V, 25 C unless otherwise stated.
Max
Unit
1
D
Bus frequency (tcyc = 1/fBus)fBus
dc
20
MHz
2
D
Internal low power oscillator period
tLPO
700
1300
s
3
D
External reset pulse width2
2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
textrst
100
ns
4
D
Reset low drive
trstdrv
66 x tcyc
——
ns
5
D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
ns
6
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
tMSH
100
s
7
D
IRQ pulse width
Asynchronous path2
Synchronous path4
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
tILIH
tIHIL
100
1.5 x tcyc
ns
8
D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH
tIHIL
100
1.5 x tcyc
ns
9
C
Port rise and fall time — (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 C to 105C.
6 Except for LCD pins in Open Drain mode.
tRise
tFall
3
30
ns
textrst
RESET PIN
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