參數(shù)資料
型號: MC9S08GW64CLK
廠商: Freescale Semiconductor
文件頁數(shù): 22/42頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 64KB FLASH 80LQFP
標準包裝: 450
系列: S08
核心處理器: S08
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,LIN,SCI,SPI
外圍設備: LCD,PWM,WDT
輸入/輸出數(shù): 45
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 16x16b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-LQFP
包裝: 托盤
Electrical Characteristics
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
29
3.10.1
Control Timing
Figure 17. Reset Timing
Table 13. Control Timing
Num
C
Rating
Symbol
Min
Typ1
1 Typical values are based on characterization data at V
DD = 3.0 V, 25C unless otherwise stated.
Max
Unit
1
D
Bus frequency (tcyc = 1/fBus)fBus
dc
20
MHz
2
D
Internal low power oscillator period
tLPO
700
1300
s
3
D
External reset pulse width2
2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
textrst
100
ns
4
D
Reset low drive
trstdrv
34 x tcyc
——
ns
5
D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
——
ns
6
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
tMSH
100
——
s
7
D
IRQ pulse width
Asynchronous path2
Synchronous path4
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
tILIH, tIHIL
100
1.5 x tcyc
ns
8
D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
ns
9
C
Port rise and fall time — Non-LCD Pins
Low output drive (PTxDS = 0) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40C to 85C.
6 Except for LCD pins in Open Drain mode.
tRise, tFall
16
23
ns
Port rise and fall time — Non-LCD Pins
High output drive (PTxDS = 1) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
5
9
ns
10
C
Voltage Regulator Recovery time
tVRR
6
10
us
t
extrst
RESET
PIN
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