
Central Processor Unit (CPU)
MC9S08GB/GT Data Sheet, Rev. 2.3
140
Freescale Semiconductor
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
Load Accumulator from
Memory
A
← (M)
0
–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A6
B6
C6
D6
E6
F6
9ED6
9EE6
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
3
5
4
LDHX #opr16i
LDHX opr8a
LDHX opr16a
LDHX ,X
LDHX oprx16,X
LDHX oprx8,X
LDHX oprx8,SP
Load Index Register (H:X)
from Memory
H:X
← (M:M + $0001)
0
––
–
IMM
DIR
EXT
IX
IX2
IX1
SP1
45
55
32
9EAE
9EBE
9ECE
9EFE
jj
kk
dd
hh ll
ee ff
ff
3
4
5
6
5
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
Load X (Index Register
Low) from Memory
X
← (M)
0
––
–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AE
BE
CE
DE
EE
FE
9EDE
9EEE
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
3
5
4
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
Logical Shift Left
(Same as ASL)
––
DIR
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
5
1
5
4
6
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
Logical Shift Right
––
0
DIR
INH
IX1
IX
SP1
34
44
54
64
74
9E64
dd
ff
5
1
5
4
6
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
Move
(M)destination ← (M)source
H:X
← (H:X) + $0001 in
IX+/DIR and DIR/IX+ Modes
0
––
–
DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR
4E
5E
6E
7E
dd dd
dd
ii
dd
5
4
5
MUL
Unsigned multiply
X:A
← (X) × (A)
–
0
–––
0 INH
42
5
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
Negate
(Two’s Complement)
M
← – (M) = $00 – (M)
A
← – (A) = $00 – (A)
X
← – (X) = $00 – (X)
M
← – (M) = $00 – (M)
M
← – (M) = $00 – (M)
M
← – (M) = $00 – (M)
––
DIR
INH
IX1
IX
SP1
30
40
50
60
70
9E60
dd
ff
5
1
5
4
6
NOP
No Operation
Uses 1 Bus Cycle
–––––– INH
9D
1
NSA
Nibble Swap
Accumulator
A
← (A[3:0]:A[7:4])
–––––– INH
62
1
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
Inclusive OR Accumulator
and Memory
A
← (A) | (M)
0
––
–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AA
BA
CA
DA
EA
FA
9EDA
9EEA
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
3
5
4
PSHA
Push Accumulator onto
Stack
Push (A); SP
← (SP) – $0001
––––– –
INH
87
2
PSHH
Push H (Index Register
High) onto Stack
Push (H); SP
← (SP) – $0001
–––––– INH
8B
2
PSHX
Push X (Index Register
Low) onto Stack
Push (X); SP
← (SP) – $0001
–––––– INH
89
2
Table 8-1. HCS08 Instruction Set Summary (Sheet 5 of 7)
Source
Form
Operation
Description
Effect
on CCR
Ad
dress
Mode
Opcode
Operand
Bus
Cyc
les
1
VH I N Z C
C
b0
b7
0
b0
b7
C
0