參數(shù)資料
型號(hào): MC9S08DZ60ACLH
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 228/416頁(yè)
文件大小: 0K
描述: IC MCU 60K FLASH 4K RAM 64-LQFP
產(chǎn)品培訓(xùn)模塊: S08D 8-Bit Microcontroller
標(biāo)準(zhǔn)包裝: 160
系列: S08
核心處理器: S08
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲(chǔ)器容量: 60KB(60K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 24x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 729 (CN2011-ZH PDF)
配用: DEMO9S08DZ60-ND - BOARD DEMO FOR MC9S08DZ60
EVB9S08DZ60-ND - BOARD EVAL FOR 9S08DZ60
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Chapter 14 Serial Communications Interface (S08SCIV4)
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
303
Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity
that is in progress must rst be completed. This includes data characters in progress, queued idle
characters, and queued break characters.
14.3.2.1
Send Break and Queued Idle
The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the
attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times
including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1.
Normally, a program would wait for TDRE to become set to indicate the last character of a message has
moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break
character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into
the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving
device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data
bits and a framing error (FE = 1) occurs.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake
up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last
character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This
action queues an idle character to be sent as soon as the shifter is available. As long as the character in the
shifter does not nish while TE = 0, the SCI transmitter never actually releases control of the TxD pin. If
there is a possibility of the shifter nishing while TE = 0, set the general-purpose I/O controls so the pin
that is shared with TxD is an output driving a logic 1. This ensures that the TxD line will look like a normal
idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE.
The length of the break character is affected by the BRK13 and M bits as shown below.
14.3.3
Receiver Functional Description
In this section, the receiver block diagram (Figure 14-3) is used as a guide for the overall receiver
functional description. Next, the data sampling technique used to reconstruct receiver data is described in
more detail. Finally, two variations of the receiver wakeup function are explained.
The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in
SCIxC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB rst), and a stop
bit of logic 1. For information about 9-bit data mode, refer to Section 14.3.5.1, “8- and 9-Bit Data Modes.”
For the remainder of this discussion, we assume the SCI is congured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already full,
the data character is transferred to the receive data register and the receive data register full (RDRF) status
Table 14-9. Break Character Length
BRK13
M
Break Character Length
0
10 bit times
0
1
11 bit times
1
0
13 bit times
1
14 bit times
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