
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
277
Register
Name
Bit 7
654321
Bit0
IDR0
R
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
W
IDR1
R
ID20
ID19
ID18
SRR(1)
1 SRR and IDE are both 1s.
ID17
ID16
ID15
W
IDR2
R
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
W
IDR3
R
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR2
2 The position of RTR differs between extended and standard indentier mapping.
W
DSR0
R
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
DSR1
R
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
DSR2
R
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
DSR3
R
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
DSR4
R
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
DSR5
R
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
DSR6
R
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
DSR7
R
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
DLR
R
DLC3
DLC2
DLC1
DLC0
W
= Unused, always read ‘x’
Figure 12-23. Receive/Transmit Message Buffer — Extended Identier Mapping