Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
263
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
Eqn. 12-1
12.3.4.1
MSCAN Receiver Flag Register (CANRFLG)
A ag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every ag has an associated interrupt enable bit in the
CANRIER register.
Table 12-7. Time Segment 2 Values
TSEG22
TSEG21
TSEG20
Time Segment 2
0
1 Tq clock cycle1
1 This setting is not valid. Please refer to Table 12-35 for valid settings. 0
1
2 Tq clock cycles
:::
:
1
0
7 Tq clock cycles
1
8 Tq clock cycles
Table 12-8. Time Segment 1 Values
TSEG13
TSEG12
TSEG11
TSEG10
Time segment 1
0
1 Tq clock cycle1
1 This setting is not valid. Please refer to Table 12-35 for valid settings. 0
1
2 Tq clock cycles1
0
1
0
3 Tq clock cycles1
0
1
4 Tq clock cycles
::::
:
1
0
15 Tq clock cycles
1
16 Tq clock cycles
76543210
R
WUPIF
CSCIF
RSTAT1
RSTAT0
TSTAT1
TSTAT0
OVRIF
RXF
W
Reset:
00000000
= Unimplemented
Figure 12-8. MSCAN Receiver Flag Register (CANRFLG)
Bit Time
Prescaler value
()
f
CANCLK
------------------------------------------------------
1
TimeSegment1
TimeSegment2
++
()
=