Serial Peripheral Interface (S08SPIV3)
MC9S08AW60 Data Sheet, Rev.1.0
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Freescale Semiconductor
check the ag bits to determine what event caused the interrupt. The service routine should also clear the
ag bit(s) before returning from the ISR (usually near the beginning of the ISR).
12.4.3
Mode Fault Detection
A mode fault occurs and the mode fault ag (MODF) becomes set when a master SPI device detects an
error on the SS pin (provided the SS pin is congured as the mode fault input signal). The SS pin is
congured to be the mode fault input signal when MSTR = 1, mode fault enable is set (MODFEN = 1),
and slave select output enable is clear (SSOE = 0).
The mode fault detection feature can be used in a system where more than one SPI device might become
a master at the same time. The error is detected when a master’s SS pin is low, indicating that some other
SPI device is trying to address this master as if it were a slave. This could indicate a harmful output driver
conict, so the mode fault logic is designed to disable all SPI output drivers when such an error is detected.
When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI conguration back
to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are
disabled.
MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPI1C1). User
software should verify the error condition has been corrected before changing the SPI back to master
mode.
12.5
Initialization/Application Information
12.5.1
SPI Module Initialization Example
12.5.1.1
Initialization Sequence
Before the SPI module can be used for communication, an initialization procedure must be carried out, as
follows:
1. Update control register 1 (SPI1C1) to enable the SPI and to control interrupt enables. This register
also sets the SPI as master or slave, determines clock phase and polarity, and congures the main
SPI options.
2. Update control register 2 (SPI1C2) to enable additional SPI functions such as the master
mode-fault function and bidirectional mode output. Other optional SPI functions are congured
here as well.
3. Update the baud rate register (SPI1BR) to set the prescaler and bit rate divisor for an SPI master.
12.5.1.2
Pseudo—Code Example
In this example, the SPI module will be set up for master mode with only transmit interrupts enabled to
run at a maximum baud rate of bus clock divided by 2. Clock phase and polarity will be set for an
active-high SPI clock where the rst edge on SPSCK occurs at the start of the rst cycle of a data transfer.