
Serial Communications Interface (S08SCIV3)
MC9S08AW60 Data Sheet, Rev.1.0
186
Freescale Semiconductor
11.2.3
SCI Control Register 2 (SCIxC2)
This register can be read or written at any time.
1
PE
Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most signicant
bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
0
PT
Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total
number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in
the data character, including the parity bit, is even.
0 Even parity.
1 Odd parity.
76543210
R
W
Reset
00000000
Figure 11-7. SCI Control Register 2 (SCIxC2)
Table 11-4. SCIxC2 Register Field Descriptions
Field
Description
7
TIE
Transmit Interrupt Enable (for TDRE)
0 Hardware interrupts from TDRE disabled (use polling).
1 Hardware interrupt requested when TDRE ag is 1.
6
TCIE
Transmission Complete Interrupt Enable (for TC)
0 Hardware interrupt requested when TC ag is 1.
1 Hardware interrupts from TC disabled (use polling).
5
RIE
Receiver Interrupt Enable (for RDRF)
0 Hardware interrupts from RDRF disabled (use polling).
1 Hardware interrupt requested when RDRF ag is 1.
4
ILIE
Idle Line Interrupt Enable (for IDLE)
0 Hardware interrupts from IDLE disabled (use polling).
1 Hardware interrupt requested when IDLE ag is 1.
3
TE
Transmitter Enable
0 Transmitter off.
1 Transmitter on.
TE must be 1 in order to use the SCI transmitter. Normally, when TE = 1, the SCI forces the TxD pin to act as an
output for the SCI system. If LOOPS = 1 and RSRC = 0, the TxD pin reverts to being a port B general-purpose
I/O pin even if TE = 1.
When the SCI is congured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of
trafc on the single SCI communication line (TxD pin).
TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress.
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued
break character nishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
Table 11-3. SCIxC1 Register Field Descriptions (continued)
Field
Description