參數(shù)資料
型號： MC9328MXLVH15
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
封裝： 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁數(shù)： 51/89頁
文件大?。?/td> 1869K
代理商： MC9328MXLVH15
Specifications
MOTOROLA
MC9328MXL Advance Information
55
3.11.2 SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the
interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data
in this mode. The memory controller generates an interrupt according to this low and the system interrupt
continues until the source is removed (SD_DAT[1] returns to its high level).
In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt
Period" during the data access, and the controller must sample SD_DAT[1] during this short period to
determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each
block (512 bytes).
Table 19. Timing Values for Figure 39 through Figure 43
Parameter
Symbol
Minimum
Maximum
Unit
Parameter
MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum
(VIL)
MMC/SD bus clock, CLK
(All values are referred to
minimum (VIH) and
maximum (VIL)
Command response cycle
NCR
2
64
Clock
cycles
Command response cycle
Identification response
cycle
NID
5
Clock
cycles
Identification response
cycle
Access time delay cycle
NAC
2
TAAC + NSAC
Clock
cycles
Access time delay cycle
Command read cycle
NRC
8
—
Clock
cycles
Command read cycle
Command-command
cycle
NCC
8
—
Clock
cycles
Command-command cycle
Command write cycle
NWR
2
—
Clock
cycles
Command write cycle
Stop transmission cycle
NST
2
Clock
cycles
Stop transmission cycle
TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC100) defined in CSD register
bit[111:104]
TAAC: Data read access
time -1 defined in CSD
register bit[119:112]
NSAC: Data read access
time -2 in CLK cycles
(NSAC100) defined in
CSD register bit[111:104]
相關(guān)PDF資料
PDF描述
MC9328MXLDVP15 150 MHz, RISC PROCESSOR, PBGA225
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MC9328MXLVF15 32-BIT, 150 MHz, RISC PROCESSOR, PBGA225
MC9328MXLVH20 32-BIT, 200 MHz, RISC PROCESSOR, PBGA256
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC9328MXLVH20 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX Integrated Portable System Processor
MC9328MXLVH20R2 制造商:Rochester Electronics LLC 功能描述:DRAGONBALL CORSICA - Bulk 制造商:Motorola Inc 功能描述:
MC9328MXLVM15 功能描述:處理器 - 專門應(yīng)用 DRAGONBALL CORSICA PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MXLVM15R2 功能描述:處理器 - 專門應(yīng)用 DRAGONBALL CORSICA PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MXLVM20 功能描述:處理器 - 專門應(yīng)用 DRAGONBALL CORSICA PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
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