參數(shù)資料
型號(hào): MC9328MXLDVF20R2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 200 MHz, RISC PROCESSOR, PBGA225
封裝: 13 X 13 MM, 0.80 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 72/82頁
文件大?。?/td> 1452K
代理商: MC9328MXLDVF20R2
74
MC9328MXL Advance Information
MOTOROLA
Specifications
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold
time and setup time, according to:
Rising-edge latch data
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
Table 31. Gated Clock Mode Timing Parameters
Ref No.
Parameter
Min
Max
Unit
1
csi_vsync to csi_hsync
180
ns
2
csi_hsync to csi_pixclk
1
ns
3
csi_d setup time
1
ns
4
csi_d hold time
1
ns
5
csi_pixclk high time
10.42
ns
6
csi_pixclk low time
10.42
ns
7
csi_pixclk frequency
0
48
MHz
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