參數(shù)資料
型號: MC9328MXLDVF15
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 150 MHz, RISC PROCESSOR, PBGA225
封裝: 13 X 13 MM, 0.80 MM PITCH, MAPBGA-225
文件頁數(shù): 64/89頁
文件大?。?/td> 1869K
代理商: MC9328MXLDVF15
Specifications
MOTOROLA
MC9328MXL Advance Information
67
3.16 I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
Figure 54. Definition of Bus Timing for I2C
3.17 Synchronous Serial Interface
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode,
the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous
mode, the transmitter and receiver each have their own clock and frame synchronization signals.
Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In
gated clock mode, the clock functions only during transmission. The internal and external clock timing
diagrams are shown in Figure 56 through Figure 58 on page 69.
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is
typically used in star or ring-time division multiplex networks with other processors or codecs, allowing
interface to time division multiplexed networks without additional logic. Use of the gated clock is not
allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to
communicate with a wide variety of devices.
Table 27. I2C Bus Timing Parameter Table
Ref No.
Parameter
1.8V ± 0.10V
3.0V ± 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
1
Hold time (repeated) START condition
182
160
ns
2
Data hold time
0171
0150
ns
3
Data setup time
11.4
10
ns
4
HIGH period of the SCL clock
80
120
ns
5
LOW period of the SCL clock
480
320
ns
6
Setup time for STOP condition
182.4
160
ns
SDA
SCL
1
2
3
4
6
5
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