參數(shù)資料
型號: MC9328MX21VKR2
廠商: Freescale Semiconductor
文件頁數(shù): 17/100頁
文件大?。?/td> 0K
描述: IC MCU I.MX21 266MHZ 289-MAPBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: i.MX21
核心處理器: ARM9
芯體尺寸: 32-位
速度: 266MHz
連通性: 1 線,EBI/EMI,I²C,IrDA,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 192
程序存儲器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.45 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 289-LFBGA
包裝: 帶卷 (TR)
Specifications
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
23
Figure 7. MMD (ATI) Drives Clock, MMD Write BMI Timing
(MMD_MODE_SEL=1, MASTER_MODE_SEL=0, MMD_CLKOUT=0)
Note:
All timings assume that the hclk is running at 133 MHz.
Note:
At this mode, the maximum frequency of the BMI_CLK/CS can be up to 36 MHz (doubles as maximum data pad speed).
3.8.1.2
BMI Drives the BMI_CLK/CS
In this mode MMD_MODE_SEL and MMD_CLKOUT are both set. The software must know which
mode it is now (READ or WRITE). When the BMI_WRITE is high, BMI drives BMI_CLK/CS out if the
TxFIFO is not emptied. When BMI_WRITE is low, user can write a 1 to READ bit of control register1 to
issue a write cycle (MMD write BMI).
3.8.1.3
MMD Read BMI Timing
Figure 13 shows the MMD read BMI timing when BMI drives the BMI_CLK/CS. When the BMI_WRITE
is high, the BMI drives BMI_CLK/CS out if data is written to TxFIFO (BMI_READ_REQ become high),
BMI puts data into data bus and enable data out on the rising edge of BMI_CLK/CS. The MMD devices
can latch the data on each falling edge of BMI_CLK/CS.
It is recommended that the MMD do not change the BMI_WRITE signal from high to low when the
BMI_READ_REQ is asserted. If user writes data to the TxFIFO when the BMI_WRITE is low, the BMI
will drive BMI_CLK/CS out once the BMI_WRITE is changed from low to high.
Table 15. MMD Write BMI Timing
Item
Symbol
Minimum
Typical
Maximum
Unit
write setup time
Ts
11
ns
write
h
old
t
ime
Th
0––
ns
receive data setup time
Tds
5
ns
Can be asserted any time
BMI_CLK/CS
BMI_READ_REQ
BMI_WRITE
BMI_D[15:0]
RxD1
RxD2
Last RxD
Ts
Tds
Th
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