參數(shù)資料
型號(hào)： MC9328MX21SVK
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 7/88頁(yè)
文件大小： 0K
描述： IC MCU I.MX21 266MHZ 289-MAPBGA
標(biāo)準(zhǔn)包裝： 152
系列： i.MX21
核心處理器： ARM9
芯體尺寸： 32-位
速度： 266MHz
連通性： 1 線，EBI/EMI，I²C，IrDA，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 192
程序存儲(chǔ)器類型： ROMless
電壓 - 電源 (Vcc/Vdd)： 1.45 V ~ 3.3 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 289-LFBGA
包裝： 托盤
Specifications
MC9328MX21S Technical Data, Rev. 1.3
Freescale Semiconductor
15
3.4
AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All
signals are specified relative to an appropriate edge of other signals. All timing specifications are specified
at a system operating frequency (HCLK) from 0 MHz to 133 MHz (core operating frequency 266 MHz)
with an operating supply voltage from V
DD min
to V
DD max
under an operating temperature from TL to TH.
All timing is measured at 30 pF loading with the exception of fast I/O signals as discussed below. Refer
to the reference manual’s System Control Chapter for details on drive strength settings.
Table 8 provides the maximum loading guidelines that can be tolerated on a memory I/O signal (also
known as Fast I/O) to achieve 133 MHz operation. These critical signals include the SDRAM Clock
(SDCLK), Data Bus signals (D[31:0]), lower order address signals such as A0-A10, MA10, MA11, and
other signals required to meet 133 MHz timing.
The values shown in Table 8 apply over the recommended operating temperature range. Care must be
taken to minimize parasitic capacitance of associated printed circuit board traces.
Table 8. Loading Guidelines for Fast IO Signals to Achieve 133 MHz Operation
Drive Strength Setting (DSCR2–DSCR12)
Maximum I/O Loading at 1.8 V
Maximum I/O Loading at 3.0 V
000: 3.5 mA
9 pF
12 pF
001: 4.5 mA
12 pF
16 pF
011: 5.5 mA
15 pF
21 pF
111: 6.5 mA
19 pF
26 pF
Table 9. 32k/26M Oscillator Signal Timing
Parameter
Minimum
RMS
Maximum
Unit
EXTAL32k input jitter (peak to peak) for both System PLL and MCUPLL
–
5
20
ns
EXTAL32k input jitter (peak to peak) for MCUPLL only
–
5
100
ns
EXTAL32k startup time
800
–
ms
Table 10. CLKO Rise/Fall Time (at 30pF Loaded)
Best Case
Typical
Worst Case
Units
Rise Time
0.80
1.00
1.40
ns
Fall Time
0.74
1.08
1.67
ns
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX21
Product
Family
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